From document US 2015/0060938 A1 there is known a method for manufacturing a power semiconductor device. The method comprises the step of providing an n-type semiconductor wafer. An edge termination structure portion is provided in a chip outer peripheral portion of regions of the n-type wafer, surrounding an active region inside a chip inner portion. In the edge termination structure an interlayer dielectric layer is formed for isolating floating field plates in the edge termination structure on a front side of the wafer. In the active region there is formed an emitter electrode on the front side of the wafer. Thereafter the back surface of the n-type wafer is uniformly ground for reducing the thickness of the n-type wafer.
From US 2014/0361312 A1 there is known a method for manufacturing a power semiconductor device including the steps of providing a p-type SiC substrate wafer, which includes an active area and an edge termination area surrounding the active area, forming a BSPG layer in the edge termination area on a front side of the wafer, forming a source electrode in the active area on the front side of the substrate wafer and performing back grinding to reduce the time required for a trench etching process for the rear surface of the substrate wafer.
From WO 2015/025625 A1 there is known silicon carbide semiconductor device and a manufacturing method for the same, in which a silicon carbide semiconductor substrate comprising a first main surface and a second main surface, is prepared. A first electrode, which is in contact with the first main surface of the silicon carbide semiconductor substrate and which is ohmically connected to the silicon carbide semiconductor substrate, is formed. At least a portion of the second main surface side of the silicon carbide semiconductor substrate is removed. A second electrode, which is in contact with the second main surface of the silicon carbide semiconductor substrate that has been exposed by the removal of the at least a portion of the silicon carbide semiconductor substrate, and which is ohmically connected to the silicon carbide semiconductor substrate, is formed. A metal layer which is in electrical contact with a fourth main surface of the second electrode is formed. The thickness of the metal layer is greater than the thickness of the silicon carbide semiconductor substrate subsequent to the removal of the at least a portion of the silicon carbide semiconductor substrate. As a result, a silicon carbide semiconductor device in which ON-resistance can be reduced, and a manufacturing method for the same, are provided.
From US 2005/233499 A1 there is known a manufacturing method for an IGBT, wherein the method comprises a step of providing a n-type semiconductor wafer, a step of forming an emitter electrode in an element formation region, a step of forming a polyimide resin film as an uppermost layer film on the surface side of the semiconductor wafer in an element isolation region and in the element formation region, and a back grinding step using a chuck table and a grinding wheel.
From JP 2003-249654 A it is known to provide a semiconductor device having constitution of an IGBT wherein switching characteristic when turning off is improved by using a simple structure and a method, and to provide its manufacturing method. Recessed surfaces are formed by grinding on one main surface of a semiconductor device on which surface an N+ buffer layer is formed.
There are known vertical power semiconductor devices such as the insulated gate bipolar transistor (IGBT) and different kind of power diodes, power metal oxide semiconductor field effect transistors (MOSFET) and bi-mode insulated gate transistors (BiGT), which have in common that in on-state of the device a current is flowing through a wafer in a vertical direction perpendicular to a wafer main side. In such power semiconductor device it is desired to have an on-state voltage as low as possible while maintaining a high blocking capability.
From EP 2 747 142 A1 it is known an IGBT and a manufacturing method for such IGBT. Therein, it is described to optimize the design of the termination area and to introduce an additional channel stopper area surrounding the termination area to optimize the blocking capability and the ruggedness of the IGBT.
A high blocking capability requires a relatively thick wafer. However, with increasing thickness of the wafer, the on-state voltage and losses are increasing. Therefore, to minimize the losses, the wafer of the device should not be thicker than the minimum thickness which is necessary to achieve a desired blocking capability. Reducing the thickness of the wafer also reduces the parasitic capacitances associated with the device. This reduces the drive requirements and speeds up the switching speeds.
For handling reasons the currently used wafers must have a minimum thickness well above 200  that prevents mechanical breakage during the production process. However, this minimum thickness would eliminate the required device performance in terms of losses for low voltage (<1.7 kV) devices. Hence a grinding step is introduced at the end of the production sequence to thin down the wafer to approximately 120  to 180  (depending on the voltage class) and to optimize for losses while maintaining the minimum thickness of the wafer to obtain the desired blocking capability.
A known grinding process for thinning a wafer 1 of an insulated gate bipolar transistor (IGBT) is illustrated in FIGS. 1 to 3. The wafer 1 has a first main side 2 (which is the front side of the wafer 1) and a second main side 3 opposite to the first main side 2. In FIG. 1 there is shown the wafer 1 with a processed front side in cross-section before the grinding step. The wafer 1 includes an active cell area 4 in a central part of the wafer 1 and a termination area 5 surrounding the active cell area 4 in an orthogonal projection onto a plane parallel to the first main side 2. A first electrode implemented as a metallization layer 6 is arranged on the first main side 2 of the wafer 1 in the active cell area 4. Therein, the metallization layer 6 is electrically connected to the wafer 1. In the termination area 5 there are formed guard rings 7 surrounding the active cell area 4. On the first main side 2 of the wafer 1, in the termination area 5, there are formed a passivation layer 9 and individual field plates 8 or metal plugs, which are electrically connected to the guard rings 7 through openings in a lower portion of the passivation layer 9. On top of the field plates 8 and the passivation layer 9 there is formed a thick polyimide passivation layer 17 arranged on the first main side 2 of the wafer 1 to cover the whole termination area 5. On the front side of the device which is the first main side 2 of the wafer 1, there are formed a plurality of cells in the active cell area 4. In case of an IGBT each cell includes a p-type base layer region 24 and an n-type emitter layer region 23 within the base layer region 24 to be separated from the remaining regions of the wafer 1 wherein the metallization layer 6 is electrically connected to the emitter layer region 23 and the base layer region 24. The base layer region 24 is separated from the relatively low doped bulk material of the wafer 1, which forms the drift layer in the final device, by an n-type enhancement layer 25 surrounding the base layer region 24 and having a higher doping concentration than the bulk material of the wafer 1. Further, there are formed a plurality of insulated gate electrodes adjacent to the first main side 2, each of which comprises an electrically conductive gate layer 21 and a first insulating layer 26 and second insulating layer 22, wherein the gate layer 21 is separated from any one of the layers in the wafer 1 by the first insulating layer 26 and from the metallization layer 6 by the second insulating layer 22.
For the grinding process, a foil 30 is laminated onto the front side topology of the device. The device is then mounted onto a chuck 31 and the wafer 1 is thinned from its second main side 3 by grinding while being pressed onto a grinding wheel 32 by the chuck 31 as shown in FIG. 2. The analysis on grinded wafers 1′ yielded thickness variations Ad exceeding 4 . The wafer 1′ is thinned the most in the termination area 5 while in contrast the active cell area 4 is thicker by roughly Ad=4 .
However, when the wafer 1′ is thinned down to a certain thickness to obtain a certain on-state voltage, the blocking capability is decreased and also the ruggedness of the device is impaired. In general it is desired to provide a power semiconductor device which has a low on-state voltage and a high blocking capability as well as a good ruggedness.
The inventors found out that in the prior art an inhomogeneous removal of silicon during the grinding step is caused by transfer of the front-side topology of the wafer to the backside during the grinding step. Especially a height difference between the metallization layer 6 in the active cell area 4 and the polyimide passivation layer 17 in the termination area 5 results in an inhomogeneous thickness of the wafer 1′ after grinding as shown in FIG. 3.